Supporting CPRI-Based Wireless Basestations with Cost Optimized FPGAs

 

Van Macomb and Ron Warner - Lattice Semiconductor Corporation

 

Introduction

 

FPGA vendors gain a unique perspective on the overall telecom/datacom market space because programmable logic devices have found their way into a broad swath of products, ranging from mass-produced set top boxes to next generation core routers.  At the same time, working closely with individual equipment vendors to implement programmable solutions provides insights into the challenges confronting infrastructure providers and the strategies that they have developed in response. 

It is clear from this vantage point that wireless infrastructure providers are beset by formidable challenges.  These challenges arise from therequirement to support multiple, competing, air interface standards and their planned evolutions for greater bandwidth and spectral efficiencies (e.g. GSM/GPRS/EDGE/UMTS or IS95A/B/CDMA20001x-RTT/1xEVDO/DV/3xRTT), fend off or absorb disruptive technologies like WIMAX, and the need to reduce costs and shorten deployment intervals.

 

 

The Role of FPGAs in Wireless Infrastructures

 

FPGAs have been part of the wireless success story since the early analog (AMPS) days nearly 25 years ago.  From simple glue logic functions and baseband filters in the early days, to more complex functions such as Digital Up Conversion, Digital Down Conversion, Crest Factor Reduction and Digital Pre-Distortion, FPGAs have been relied upon for their flexibility and time to market advantage.  Indeed, the architecture of FPGAs themselves was influenced by the needs of the wireless community.  The incorporation of embedded DSP blocks, embedded Memory and SERDES dovetailed with the evolving needs of wireless equipment providers.

 

The greatest challenge facing the wireless industry today is the need to provide greater bandwidth.  Raw subscriber growth and MOUs (Minutes of Use) have been the perennial growth engines for the wireless industry, but this growth rate has tapered off in recent years.  The new growth engine has been defined as the value chain that delivers new services such as on demand video and music, traffic and mapping services, streaming audio/video, broadcast video and even TV.  As a result, the ability to support ever-increasing data rates under extreme pressure to reduce costs is critical.

 

Common Public Radio Interface (CPRI)

 

In response to these demands, CPRI was formed in 2003 as an industry initiative to define a common interface between radio equipment (RE) and their controllers (REC).  By standardizing or opening this interface, these two components from different vendors can be mixed and matched, which reduces development costs, simplifies integration, and broadens a vendor's product offering to network operators.  In addition, CPRI specifies a high-speed serial interface between the RE and REC in order to support the demand for greater bandwidth. 

 

Evolution of Base Station Deployment Under CPRI

 

Traditional Base Station Deployment

Traditional base station deployment has seen the BTS co-located with the antenna tower in a single enclosure.  This co-located architecture was necessary to minimize the loss suffered over the electrical cable connection between the tower and the BTS.  In support of this type of deployment, the original topologies of CPRI were all defined with a direct connection from the antenna or RE (Radio Equipment) to the REC (Radio Equipment Controller) at the base station.  Figure 1 shows the traditional base station deployment and CPRI support.

 

 

 

Figure 1 - Traditional Base Station Topology

 

 

While arguably simpler from a control perspective, the co-located approach has proven to be detrimental to the providers in terms of the large footprint, high power and ultimately high cost of its deployment.  It was clear that operators needed a new approach to base station distribution that would reduce the overall cost of system deployment and operation.

 

Distributed Base Station Architecture

One obvious approach was to eliminate the dependency of the RF transceivers on the rest of the base station, allowing them to be relocated next to their respective antennas, as shown in Figure 2.  However, to do so would require a means to transport the baseband data to these remote locations and to do so without the cost of additional power amplification. The CPRI protocol has addressed the needs of RRH (Remote Radio Head) networking in its recent specification.

 

Distributed Architecture Control Requirements

A key enabling factor for CPRI in terms of supporting these topologies is the C&M (Control and Messaging) sub-channels that are defined as part of the specification.  There are two approaches defined, a slow C&M based on the HDLC protocol and an Ethernet-based fast C&M channeEach option has pros and cons, but the fast C&M sub-channel is gaining momentum, since it offers higher bandwidth and is encapsulated in standard Ethernet frames that are recognizable by higher layer MAC (Media Access Controller) processing.  Routing of this control information must be done at each intermediate RRH, meaning each RE can take advantage of the ubiquitous nature of IP-based switching hardware and software solutions to perform the necessary routing of the control messages to subsequent nodes.  FPGA implementations offer a low cost, flexible approach that supports both C&M schemes.  Using an FPGA also provides the ability to migrate between these two control planes in support of evolving topologies with little or no impact on system level hardware.

 

 

 

 

 

 

Figure 2 - Distributed Base Station Topologies

 

 

CPRI Protocol Up Close

 

The nature of deploying REs remotely requires that the interface be capable of not only data transport, but also be able to communicate both control and synchronization information over the same interface.  CPRI defines a point-to-point digital interface between the REC and the REs that contains both a physical layer and data link layer to address this requirement (Figure 3).

 

Figure 3 - System and Interface Definition

 

 

Looking more closely at the CPRI protocol stack (Figure 4), the inherent capabilities that allow support of distributed base station deployment can be seen.  The physical layer (layer 1) supports serial data rates of up to 3Gbps, providing adequate bandwidth for emerging wireless standards and applications, while the data link layer (layer 2) defines the user payload, the Control and Management (C&M) plane and link synchronization. It is this data link layer processing capability that is the key to providing the necessary data transport and control mechanisms in support of RRH deployment. Both fast and slow C&M channels are supported, but as more REs are networked under this remote deployment, the fast C&M Ethernet channel has emerged as the control plane of choice due to its increased bandwidth.

 

Figure 4 - CPRI Protocol Stack

 

 

Implementing CPRI in Low Cost FPGAs

 

Until recently, equipment vendors that wanted an FPGA implementation had to select premium FPGA product because these were the only devices that offered the embedded SERDES needed to support the Physical Medium Attachment (PMA) requirements of CPRIThe advent of low cost FPGAs with similar SERDES capabilities is a recent and rule-changing concept. An example of this is the LatticeECP2M low cost FPGA. Regardless of cost, any FPGA that plays in the Remote Radio Head application space must support the Physical Link layer (layer 1) and the Data Link layer (layer 2) of the CPRI specification.

It also must support the four standard bit rates of the CPRI v3.0 specification (614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps and 3072 Mbps)

The solution should also perform CPRI compliant Hyperframe framing, including:

 

·                     Interleaving of I/Q data, sync, C&M data and vendor specific information into frame/hyperframe formats

·                     Provide flexible parallel interface for I/Q data

·                     Perform sub-channel mapping by supporting the fast C&M channel (21.12/42.24/84.48 Mbps) based on an Ethernet interface to the user logic and accepts a user-selected pointer to the CPRI sub-channel where the Ethernet link starts.

·                     Support the optional slow C&M channel based on a serial HDLC interface at standard bit rates (240 Kbps, 480 Kbps, 960 Kbps, and 1920 Kbps)

·                     Perform synchronization and timing as defined in section 4.2.8 of the CPRI Specification.

·                     Support L1 Inband Protocol for link control/maintenance.

·                     Provide a parallel interface for merging vendor specific data into the CPRI frame.

·                     Provide a start-up sequence state machine in hardware for both REC and RE nodes which performs:

§   Synchronization and Rate Negotiation

§   C&M Plane Setup

·                     Perform Link Maintenance as defined in section 4.2.10 of the CPRI Specification:

§   LOS Detection

§   LOF Detection

§   RAI Indication

 

An FPGA implementation with the CPRI solution divided into hard and soft IP, as well as user specific logic, is shown in Figure 5.

Figure 5 - Partitioning of CPRI Protocol Stack

 

The Advantage of Programmability

 

As with any emerging standard or technology, vendors rarely follow these specifications to the letter, choosing instead to architect their systems utilizing proprietary circuitry that augments the functionality called for in the specification… a way to differentiate themselves and implement value-added features to their final product

 

The advantages of stand-alone ASSPs are well documented and understood.  However, for applications involving emerging specifications, or where custom logic is desired, programmability is a key advantage and also a necessity for the designer.  Programmability offers system designers the luxury to incorporate vendor- specific logic in the RRH Application Layer, and at the same time provides the flexibility to provide multi-regional solutions for deployment of planned evolutions (e.g. GSM/GPRS/EDGE/UMTS), as well as test newer standards such as WiMAX and LTE.  One such solution is the LatticeECP2M family of FPGAs. The ASIC portion of the device offers performance and power advantages for the “fixed” logic such as the physical layer of the CPRI specification, including integrated high speed SERDES channels, and encode/decode logic.  Programmable logic provides the flexibility to customize vendor specific or parametrizable portions of the data link layer and control plane, which is commonly where designs are modified in response to changing specifications and customer requirements. Additionally, trends will emerge whereby the CPRI implementation will integrate with RE and REC processing modules in single monolithic chips. Low cost FPGAs now provide the necessary SERDES, programmable logic, and DSP functionality to help achieve this integration at price points and footprints that were previously unachievable with high end FPGAs or ASSP/FPGA combinations.

 

Conclusion

 

CPRI was originally defined as an open standard, specifically targeting the REC to RE interface with the intent of reducing system hardware costs while providing the bandwidth necessary to support many evolving 3G/4G applications.  The original CPRI specification was later updated and can now be teamed with loss-free optical fiber (as the physical medium) to enable the evolution of base station deployment to a more distributed model, where a single REC is capable of serving many less expensive, lower power, remote radio heads. 

 

Wireless equipment vendors have relied on FPGAs to implement multiple functions as wireless technology has evolved.  CPRI is one example of a wireless protocol that is both new and evolving, and one that can be fully supported in FPGAs.  The advantages of using a flexible, low cost FPGA based implementation are many.  They include rapid time to market, the ability to accommodate changes in the specification without modifying hardware, flexibility to implement differentiating features and integrating multiple functionality onto one chip, all at cost points that enable high volume deployment.  In the case of CPRI, the ability to support the flexible and parametrizable C&M channels and customer specific applications layers emphatically demonstrates why the programmable nature of FPGAs provides the ideal platform for this implementation, as it allows the sub-channel and upper layer MAC functionality to be integrated on the same low cost device.